1. Field of the Invention
The present invention relates to a three-dimensional memory chip package structure. More particularly, the present invention relates to a three-dimensional memory chip package structure having zigzag-arranged, dual-row bond pad layout on the die thereof.
2. Description of the Prior Art
As known in the art, the bond pads of a memory chip are ordinarily designed and disposed at a central region of the chip and are arranged side by side in two rows in order to accommodate conventional window ball grid array (wBGA) configuration for single-die packaging. FIG. 1 is a schematic, cross-sectional view showing a typical wBGA package structure. As shown in FIG. 1, a die is flipped face-down and mounted on a substrate having a window therein. The bond pads A and bond pads B of the die, which are arranged in two rows in a side-by-side manner, are wire bonded to respective bond pads on a bottom surface of the substrate through the window. The bond pads A and bond pads B are electrically connected the corresponding solder balls A and B by way of circuit tracing formed in the substrate. Further, it is known that the package bailout of DDR-SDRAM package or module has to consist with the JEDEC standards.
The industry has developed various DRAM package technologies in recent years. For example, three-dimensional package technology utilizing wire bonding can be employed in high-capacity DRAM modules. FIG. 2 is a schematic, cross-sectional diagram illustrating a conventional three-dimensional memory module 1. As show in FIG. 2, the three-dimensional memory module 1 comprises a die 20 mounted face-up on a carrier substrate 10 and a die 30 stacked on the die 20. The die 20 is affixed to the carrier substrate 10 using an adhesive layer 42. The die 30 is affixed on the die 20 using an adhesive layer 52. The bond pad A denoted by numeral number 22 of the die 20 is electrically connected to the bond finger 102 on a top surface 10a of the carrier substrate 10 through the bone wire 122, while the bond pad B denoted by numeral number 24 is electrically connected to the bond finger 104 on a top surface 10a of the carrier substrate 10 through the bone wire 124. Likewise, the bond pad A denoted by numeral number 32 of the die 30 is electrically connected to the bond finger 102 on a top surface 10a of the carrier substrate 10 through the bone wire 132, while the bond pad B denoted by numeral number 34 is electrically connected to the bond finger 104 on a top surface 10a of the carrier substrate 10 through the bone wire 134.
As aforementioned, since the package bailout of DDR-SDRAM module has to consist with the JEDEC standards, a longer wire tracing path 106 in the carrier substrate 10 is required to electrically connect the corresponding bond pad A denoted by numeral number 22 or 32 to the solder ball A on the bottom surface 10b of the carrier substrate 10 and a longer wire tracing path 108 in the carrier substrate 10 is required to electrically connect the bond pad B denoted by numeral number 24 or 34 to the corresponding solder ball B on the bottom surface 10b of the carrier substrate 10. The longer wire tracing paths 106 and 108 result in decreased chip performance in terms of increase of resistance, inductance or capacitance, and increased signal noise.
In light of the above, there is a strong need in this industry to provide an improved three-dimensional DRAM packaging technology in order to solve the above-mentioned problems.